// Copyright (C) 1953-2022 NUDT
// Verilog module name - input_convergence_adaptation 
// Version:V4.0.0.20220524
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         send the descriptor delayed
//         avoid reading pkt data before it is written to the bufm
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module input_convergence_adaptation
(
        i_clk           ,
        i_rst_n         ,
        
        iv_md_p0        ,
        i_md_wr_p0      ,
        o_md_ack_p0     ,
        
        iv_md_p1        ,
        i_md_wr_p1      ,
        o_md_ack_p1     ,
        
        iv_md_p2        ,
        i_md_wr_p2      ,
        o_md_ack_p2     ,

        iv_md_p3        ,
        i_md_wr_p3      ,
        o_md_ack_p3     , 
        
        iv_md_p4,
        i_md_wr_p4,
        o_md_ack_p4,    
        
        iv_md_p5,
        i_md_wr_p5,
        o_md_ack_p5,    
        
        iv_md_p6,
        i_md_wr_p6,
        o_md_ack_p6,    
        
        iv_md_p7,
        i_md_wr_p7,
        o_md_ack_p7,    
        
        iv_md_p8,
        i_md_wr_p8,
        o_md_ack_p8,    
        
        iv_md_p9,
        i_md_wr_p9,
        o_md_ack_p9,    
        
        iv_md_p10,
        i_md_wr_p10,
        o_md_ack_p10,    
        
        iv_md_p11,
        i_md_wr_p11,
        o_md_ack_p11,    
        
        iv_md_p12,
        i_md_wr_p12,
        o_md_ack_p12,    
        
        iv_md_p13,
        i_md_wr_p13,
        o_md_ack_p13,    
        
        iv_md_p14,
        i_md_wr_p14,
        o_md_ack_p14,    
        
        iv_md_p15,
        i_md_wr_p15,
        o_md_ack_p15,    
        
        iv_md_p16,
        i_md_wr_p16,
        o_md_ack_p16,    
        
        iv_md_p17,
        i_md_wr_p17,
        o_md_ack_p17,    
        
        iv_md_p18,
        i_md_wr_p18,
        o_md_ack_p18,    
        
        iv_md_p19,
        i_md_wr_p19,
        o_md_ack_p19,    
        
        iv_md_p20,
        i_md_wr_p20,
        o_md_ack_p20,    
        
        iv_md_p21,
        i_md_wr_p21,
        o_md_ack_p21,    
        
        iv_md_p22,
        i_md_wr_p22,
        o_md_ack_p22,    
        
        iv_md_p23,
        i_md_wr_p23,
        o_md_ack_p23,    
        
        iv_md_p24,
        i_md_wr_p24,
        o_md_ack_p24,    
        
        iv_md_p25,
        i_md_wr_p25,
        o_md_ack_p25,    
        
        iv_md_p26,
        i_md_wr_p26,
        o_md_ack_p26,    
        
        iv_md_p27,
        i_md_wr_p27,
        o_md_ack_p27,    
        
        iv_md_p28,
        i_md_wr_p28,
        o_md_ack_p28,    
        
        iv_md_p29,
        i_md_wr_p29,
        o_md_ack_p29,    
        
        iv_md_p30,
        i_md_wr_p30,
        o_md_ack_p30,    
        
        iv_md_p31,
        i_md_wr_p31,
        o_md_ack_p31,            
        
        iv_md_p32,
        i_md_wr_p32,
        o_md_ack_p32, 

        ov_md           , 
        o_md_wr         
);

// I/O
// clk & rst
input                  i_clk  ;                   //125Mhz
input                  i_rst_n;

input      [299:0]     iv_md_p0     ;
input                  i_md_wr_p0   ;
output                 o_md_ack_p0  ;

input      [299:0]     iv_md_p1     ;
input                  i_md_wr_p1   ;
output                 o_md_ack_p1  ;

input      [299:0]     iv_md_p2     ;
input                  i_md_wr_p2   ;
output                 o_md_ack_p2  ;

input      [299:0]     iv_md_p3     ;
input                  i_md_wr_p3   ;
output                 o_md_ack_p3  ;
       
input      [299:0]     iv_md_p4;
input                  i_md_wr_p4;
output                 o_md_ack_p4;    

input      [299:0]     iv_md_p5;
input                  i_md_wr_p5;
output                 o_md_ack_p5;    

input      [299:0]     iv_md_p6;
input                  i_md_wr_p6;
output                 o_md_ack_p6;    

input      [299:0]     iv_md_p7;
input                  i_md_wr_p7;
output                 o_md_ack_p7;    

input      [299:0]     iv_md_p8;
input                  i_md_wr_p8;
output                 o_md_ack_p8;    

input      [299:0]     iv_md_p9;
input                  i_md_wr_p9;
output                 o_md_ack_p9;    

input      [299:0]     iv_md_p10;
input                  i_md_wr_p10;
output                 o_md_ack_p10;    

input      [299:0]     iv_md_p11;
input                  i_md_wr_p11;
output                 o_md_ack_p11;    

input      [299:0]     iv_md_p12;
input                  i_md_wr_p12;
output                 o_md_ack_p12;    

input      [299:0]     iv_md_p13;
input                  i_md_wr_p13;
output                 o_md_ack_p13;    

input      [299:0]     iv_md_p14;
input                  i_md_wr_p14;
output                 o_md_ack_p14;    

input      [299:0]     iv_md_p15;
input                  i_md_wr_p15;
output                 o_md_ack_p15;    

input      [299:0]     iv_md_p16;
input                  i_md_wr_p16;
output                 o_md_ack_p16;    

input      [299:0]     iv_md_p17;
input                  i_md_wr_p17;
output                 o_md_ack_p17;    

input      [299:0]     iv_md_p18;
input                  i_md_wr_p18;
output                 o_md_ack_p18;    

input      [299:0]     iv_md_p19;
input                  i_md_wr_p19;
output                 o_md_ack_p19;    

input      [299:0]     iv_md_p20;
input                  i_md_wr_p20;
output                 o_md_ack_p20;    

input      [299:0]     iv_md_p21;
input                  i_md_wr_p21;
output                 o_md_ack_p21;    

input      [299:0]     iv_md_p22;
input                  i_md_wr_p22;
output                 o_md_ack_p22;    

input      [299:0]     iv_md_p23;
input                  i_md_wr_p23;
output                 o_md_ack_p23;    

input      [299:0]     iv_md_p24;
input                  i_md_wr_p24;
output                 o_md_ack_p24;    

input      [299:0]     iv_md_p25;
input                  i_md_wr_p25;
output                 o_md_ack_p25;    

input      [299:0]     iv_md_p26;
input                  i_md_wr_p26;
output                 o_md_ack_p26;    

input      [299:0]     iv_md_p27;
input                  i_md_wr_p27;
output                 o_md_ack_p27;    

input      [299:0]     iv_md_p28;
input                  i_md_wr_p28;
output                 o_md_ack_p28;    

input      [299:0]     iv_md_p29;
input                  i_md_wr_p29;
output                 o_md_ack_p29;    

input      [299:0]     iv_md_p30;
input                  i_md_wr_p30;
output                 o_md_ack_p30;    

input      [299:0]     iv_md_p31;
input                  i_md_wr_p31;
output                 o_md_ack_p31;            

input      [299:0]     iv_md_p32;
input                  i_md_wr_p32;
output                 o_md_ack_p32;

output     [299:0]     ov_md      ;        
output                 o_md_wr    ;

wire       [299:0]     wv_md_p0_ddm2tdm;   
wire                   w_md_wr_p0_ddm2tdm; 
wire                   w_md_ack_p0_tdm2ddm;

wire       [299:0]     wv_md_p1_ddm2tdm;   
wire                   w_md_wr_p1_ddm2tdm; 
wire                   w_md_ack_p1_tdm2ddm;

wire       [299:0]     wv_md_p2_ddm2tdm;   
wire                   w_md_wr_p2_ddm2tdm; 
wire                   w_md_ack_p2_tdm2ddm;

wire       [299:0]     wv_md_p3_ddm2tdm;   
wire                   w_md_wr_p3_ddm2tdm; 
wire                   w_md_ack_p3_tdm2ddm;

wire       [299:0]     wv_md_p4_ddm2tdm;   
wire                   w_md_wr_p4_ddm2tdm; 
wire                   w_md_ack_p4_tdm2ddm;

wire       [299:0]     wv_md_p5_ddm2tdm;   
wire                   w_md_wr_p5_ddm2tdm; 
wire                   w_md_ack_p5_tdm2ddm;

wire       [299:0]     wv_md_p6_ddm2tdm;   
wire                   w_md_wr_p6_ddm2tdm; 
wire                   w_md_ack_p6_tdm2ddm;

wire       [299:0]     wv_md_p7_ddm2tdm;   
wire                   w_md_wr_p7_ddm2tdm; 
wire                   w_md_ack_p7_tdm2ddm;

wire       [299:0]     wv_md_p8_ddm2tdm;   
wire                   w_md_wr_p8_ddm2tdm; 
wire                   w_md_ack_p8_tdm2ddm;

wire       [299:0]     wv_md_p9_ddm2tdm;   
wire                   w_md_wr_p9_ddm2tdm; 
wire                   w_md_ack_p9_tdm2ddm;

wire       [299:0]     wv_md_p10_ddm2tdm;   
wire                   w_md_wr_p10_ddm2tdm; 
wire                   w_md_ack_p10_tdm2ddm;

wire       [299:0]     wv_md_p11_ddm2tdm;   
wire                   w_md_wr_p11_ddm2tdm; 
wire                   w_md_ack_p11_tdm2ddm;

wire       [299:0]     wv_md_p12_ddm2tdm;   
wire                   w_md_wr_p12_ddm2tdm; 
wire                   w_md_ack_p12_tdm2ddm;

wire       [299:0]     wv_md_p13_ddm2tdm;   
wire                   w_md_wr_p13_ddm2tdm; 
wire                   w_md_ack_p13_tdm2ddm;

wire       [299:0]     wv_md_p14_ddm2tdm;   
wire                   w_md_wr_p14_ddm2tdm; 
wire                   w_md_ack_p14_tdm2ddm;

wire       [299:0]     wv_md_p15_ddm2tdm;   
wire                   w_md_wr_p15_ddm2tdm; 
wire                   w_md_ack_p15_tdm2ddm;

wire       [299:0]     wv_md_p16_ddm2tdm;   
wire                   w_md_wr_p16_ddm2tdm; 
wire                   w_md_ack_p16_tdm2ddm;

wire       [299:0]     wv_md_p17_ddm2tdm;   
wire                   w_md_wr_p17_ddm2tdm; 
wire                   w_md_ack_p17_tdm2ddm;

wire       [299:0]     wv_md_p18_ddm2tdm;   
wire                   w_md_wr_p18_ddm2tdm; 
wire                   w_md_ack_p18_tdm2ddm;

wire       [299:0]     wv_md_p19_ddm2tdm;   
wire                   w_md_wr_p19_ddm2tdm; 
wire                   w_md_ack_p19_tdm2ddm;

wire       [299:0]     wv_md_p20_ddm2tdm;   
wire                   w_md_wr_p20_ddm2tdm; 
wire                   w_md_ack_p20_tdm2ddm;

wire       [299:0]     wv_md_p21_ddm2tdm;   
wire                   w_md_wr_p21_ddm2tdm; 
wire                   w_md_ack_p21_tdm2ddm;

wire       [299:0]     wv_md_p22_ddm2tdm;   
wire                   w_md_wr_p22_ddm2tdm; 
wire                   w_md_ack_p22_tdm2ddm;

wire       [299:0]     wv_md_p23_ddm2tdm;   
wire                   w_md_wr_p23_ddm2tdm; 
wire                   w_md_ack_p23_tdm2ddm;

wire       [299:0]     wv_md_p24_ddm2tdm;   
wire                   w_md_wr_p24_ddm2tdm; 
wire                   w_md_ack_p24_tdm2ddm;

wire       [299:0]     wv_md_p25_ddm2tdm;   
wire                   w_md_wr_p25_ddm2tdm; 
wire                   w_md_ack_p25_tdm2ddm;

wire       [299:0]     wv_md_p26_ddm2tdm;   
wire                   w_md_wr_p26_ddm2tdm; 
wire                   w_md_ack_p26_tdm2ddm;

wire       [299:0]     wv_md_p27_ddm2tdm;   
wire                   w_md_wr_p27_ddm2tdm; 
wire                   w_md_ack_p27_tdm2ddm;

wire       [299:0]     wv_md_p28_ddm2tdm;   
wire                   w_md_wr_p28_ddm2tdm; 
wire                   w_md_ack_p28_tdm2ddm;

wire       [299:0]     wv_md_p29_ddm2tdm;   
wire                   w_md_wr_p29_ddm2tdm; 
wire                   w_md_ack_p29_tdm2ddm;

wire       [299:0]     wv_md_p30_ddm2tdm;   
wire                   w_md_wr_p30_ddm2tdm; 
wire                   w_md_ack_p30_tdm2ddm;

wire       [299:0]     wv_md_p31_ddm2tdm;   
wire                   w_md_wr_p31_ddm2tdm; 
wire                   w_md_ack_p31_tdm2ddm;

wire       [299:0]     wv_md_p32_ddm2tdm;   
wire                   w_md_wr_p32_ddm2tdm; 
wire                   w_md_ack_p32_tdm2ddm;

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p0_inst(                              
.i_clk                  (i_clk      ),
.i_rst_n                (i_rst_n    ),
                                
.iv_md                  (iv_md_p0   ),
.i_md_wr                (i_md_wr_p0 ),
.o_md_ack               (o_md_ack_p0),
                                
.ov_md                  (wv_md_p0_ddm2tdm   ),
.o_md_wr                (w_md_wr_p0_ddm2tdm ),
.i_md_ack               (w_md_ack_p0_tdm2ddm)
);
                                
diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p1_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p1),
.i_md_wr                (i_md_wr_p1),
.o_md_ack               (o_md_ack_p1),
                                
.ov_md                  (wv_md_p1_ddm2tdm),
.o_md_wr                (w_md_wr_p1_ddm2tdm),
.i_md_ack               (w_md_ack_p1_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p2_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p2),
.i_md_wr                (i_md_wr_p2),
.o_md_ack               (o_md_ack_p2),
                                
.ov_md                  (wv_md_p2_ddm2tdm),
.o_md_wr                (w_md_wr_p2_ddm2tdm),
.i_md_ack               (w_md_ack_p2_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p3_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p3),
.i_md_wr                (i_md_wr_p3),
.o_md_ack               (o_md_ack_p3),
                                
.ov_md                  (wv_md_p3_ddm2tdm),
.o_md_wr                (w_md_wr_p3_ddm2tdm),
.i_md_ack               (w_md_ack_p3_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p4_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p4),
.i_md_wr                (i_md_wr_p4),
.o_md_ack               (o_md_ack_p4),
                                
.ov_md                  (wv_md_p4_ddm2tdm),
.o_md_wr                (w_md_wr_p4_ddm2tdm),
.i_md_ack               (w_md_ack_p4_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p5_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p5),
.i_md_wr                (i_md_wr_p5),
.o_md_ack               (o_md_ack_p5),
                                
.ov_md                  (wv_md_p5_ddm2tdm),
.o_md_wr                (w_md_wr_p5_ddm2tdm),
.i_md_ack               (w_md_ack_p5_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p6_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p6),
.i_md_wr                (i_md_wr_p6),
.o_md_ack               (o_md_ack_p6),
                                
.ov_md                  (wv_md_p6_ddm2tdm),
.o_md_wr                (w_md_wr_p6_ddm2tdm),
.i_md_ack               (w_md_ack_p6_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p7_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p7),
.i_md_wr                (i_md_wr_p7),
.o_md_ack               (o_md_ack_p7),
                                
.ov_md                  (wv_md_p7_ddm2tdm),
.o_md_wr                (w_md_wr_p7_ddm2tdm),
.i_md_ack               (w_md_ack_p7_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p8_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p8),
.i_md_wr                (i_md_wr_p8),
.o_md_ack               (o_md_ack_p8),
                                
.ov_md                  (wv_md_p8_ddm2tdm),
.o_md_wr                (w_md_wr_p8_ddm2tdm),
.i_md_ack               (w_md_ack_p8_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p9_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p9),
.i_md_wr                (i_md_wr_p9),
.o_md_ack               (o_md_ack_p9),
                                
.ov_md                  (wv_md_p9_ddm2tdm),
.o_md_wr                (w_md_wr_p9_ddm2tdm),
.i_md_ack               (w_md_ack_p9_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p10_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p10),
.i_md_wr                (i_md_wr_p10),
.o_md_ack               (o_md_ack_p10),
                                
.ov_md                  (wv_md_p10_ddm2tdm),
.o_md_wr                (w_md_wr_p10_ddm2tdm),
.i_md_ack               (w_md_ack_p10_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p11_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p11),
.i_md_wr                (i_md_wr_p11),
.o_md_ack               (o_md_ack_p11),
                                
.ov_md                  (wv_md_p11_ddm2tdm),
.o_md_wr                (w_md_wr_p11_ddm2tdm),
.i_md_ack               (w_md_ack_p11_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p12_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p12),
.i_md_wr                (i_md_wr_p12),
.o_md_ack               (o_md_ack_p12),
                                
.ov_md                  (wv_md_p12_ddm2tdm),
.o_md_wr                (w_md_wr_p12_ddm2tdm),
.i_md_ack               (w_md_ack_p12_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p13_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p13),
.i_md_wr                (i_md_wr_p13),
.o_md_ack               (o_md_ack_p13),
                                
.ov_md                  (wv_md_p13_ddm2tdm),
.o_md_wr                (w_md_wr_p13_ddm2tdm),
.i_md_ack               (w_md_ack_p13_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p14_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p14),
.i_md_wr                (i_md_wr_p14),
.o_md_ack               (o_md_ack_p14),
                                
.ov_md                  (wv_md_p14_ddm2tdm),
.o_md_wr                (w_md_wr_p14_ddm2tdm),
.i_md_ack               (w_md_ack_p14_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p15_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p15),
.i_md_wr                (i_md_wr_p15),
.o_md_ack               (o_md_ack_p15),
                                
.ov_md                  (wv_md_p15_ddm2tdm),
.o_md_wr                (w_md_wr_p15_ddm2tdm),
.i_md_ack               (w_md_ack_p15_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p16_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p16),
.i_md_wr                (i_md_wr_p16),
.o_md_ack               (o_md_ack_p16),
                                
.ov_md                  (wv_md_p16_ddm2tdm),
.o_md_wr                (w_md_wr_p16_ddm2tdm),
.i_md_ack               (w_md_ack_p16_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p17_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p17),
.i_md_wr                (i_md_wr_p17),
.o_md_ack               (o_md_ack_p17),
                                
.ov_md                  (wv_md_p17_ddm2tdm),
.o_md_wr                (w_md_wr_p17_ddm2tdm),
.i_md_ack               (w_md_ack_p17_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p18_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p18),
.i_md_wr                (i_md_wr_p18),
.o_md_ack               (o_md_ack_p18),
                                
.ov_md                  (wv_md_p18_ddm2tdm),
.o_md_wr                (w_md_wr_p18_ddm2tdm),
.i_md_ack               (w_md_ack_p18_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p19_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p19),
.i_md_wr                (i_md_wr_p19),
.o_md_ack               (o_md_ack_p19),
                                
.ov_md                  (wv_md_p19_ddm2tdm),
.o_md_wr                (w_md_wr_p19_ddm2tdm),
.i_md_ack               (w_md_ack_p19_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p20_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p20),
.i_md_wr                (i_md_wr_p20),
.o_md_ack               (o_md_ack_p20),
                                
.ov_md                  (wv_md_p20_ddm2tdm),
.o_md_wr                (w_md_wr_p20_ddm2tdm),
.i_md_ack               (w_md_ack_p20_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p21_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p21),
.i_md_wr                (i_md_wr_p21),
.o_md_ack               (o_md_ack_p21),
                                
.ov_md                  (wv_md_p21_ddm2tdm),
.o_md_wr                (w_md_wr_p21_ddm2tdm),
.i_md_ack               (w_md_ack_p21_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p22_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p22),
.i_md_wr                (i_md_wr_p22),
.o_md_ack               (o_md_ack_p22),
                                
.ov_md                  (wv_md_p22_ddm2tdm),
.o_md_wr                (w_md_wr_p22_ddm2tdm),
.i_md_ack               (w_md_ack_p22_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p23_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p23),
.i_md_wr                (i_md_wr_p23),
.o_md_ack               (o_md_ack_p23),
                                
.ov_md                  (wv_md_p23_ddm2tdm),
.o_md_wr                (w_md_wr_p23_ddm2tdm),
.i_md_ack               (w_md_ack_p23_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p24_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p24),
.i_md_wr                (i_md_wr_p24),
.o_md_ack               (o_md_ack_p24),
                                
.ov_md                  (wv_md_p24_ddm2tdm),
.o_md_wr                (w_md_wr_p24_ddm2tdm),
.i_md_ack               (w_md_ack_p24_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p25_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p25),
.i_md_wr                (i_md_wr_p25),
.o_md_ack               (o_md_ack_p25),
                                
.ov_md                  (wv_md_p25_ddm2tdm),
.o_md_wr                (w_md_wr_p25_ddm2tdm),
.i_md_ack               (w_md_ack_p25_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p26_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p26),
.i_md_wr                (i_md_wr_p26),
.o_md_ack               (o_md_ack_p26),
                                
.ov_md                  (wv_md_p26_ddm2tdm),
.o_md_wr                (w_md_wr_p26_ddm2tdm),
.i_md_ack               (w_md_ack_p26_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p27_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p27),
.i_md_wr                (i_md_wr_p27),
.o_md_ack               (o_md_ack_p27),
                                
.ov_md                  (wv_md_p27_ddm2tdm),
.o_md_wr                (w_md_wr_p27_ddm2tdm),
.i_md_ack               (w_md_ack_p27_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p28_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p28),
.i_md_wr                (i_md_wr_p28),
.o_md_ack               (o_md_ack_p28),
                                
.ov_md                  (wv_md_p28_ddm2tdm),
.o_md_wr                (w_md_wr_p28_ddm2tdm),
.i_md_ack               (w_md_ack_p28_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p29_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p29),
.i_md_wr                (i_md_wr_p29),
.o_md_ack               (o_md_ack_p29),
                                
.ov_md                  (wv_md_p29_ddm2tdm),
.o_md_wr                (w_md_wr_p29_ddm2tdm),
.i_md_ack               (w_md_ack_p29_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p30_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p30),
.i_md_wr                (i_md_wr_p30),
.o_md_ack               (o_md_ack_p30),
                                
.ov_md                  (wv_md_p30_ddm2tdm),
.o_md_wr                (w_md_wr_p30_ddm2tdm),
.i_md_ack               (w_md_ack_p30_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p31_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p31),
.i_md_wr                (i_md_wr_p31),
.o_md_ack               (o_md_ack_p31),
                                
.ov_md                  (wv_md_p31_ddm2tdm),
.o_md_wr                (w_md_wr_p31_ddm2tdm),
.i_md_ack               (w_md_ack_p31_tdm2ddm)
);

diagest_delay_manage #(.delay_cycle(4'd15)) diagest_delay_manage_p32_inst(                              
.i_clk                  (i_clk),
.i_rst_n                (i_rst_n),
                                
.iv_md                  (iv_md_p32),
.i_md_wr                (i_md_wr_p32),
.o_md_ack               (o_md_ack_p32),
                                
.ov_md                  (wv_md_p32_ddm2tdm),
.o_md_wr                (w_md_wr_p32_ddm2tdm),
.i_md_ack               (w_md_ack_p32_tdm2ddm)
);

time_division_multiplexing time_division_multiplexing_inst(
.i_clk                  (i_clk                      ),
.i_rst_n                (i_rst_n                    ),
                                                           
.iv_md_p0               (wv_md_p0_ddm2tdm           ),
.i_md_wr_p0             (w_md_wr_p0_ddm2tdm         ),
.o_md_ack_p0            (w_md_ack_p0_tdm2ddm        ),
                                                         
.iv_md_p1               (wv_md_p1_ddm2tdm           ),
.i_md_wr_p1             (w_md_wr_p1_ddm2tdm         ),
.o_md_ack_p1            (w_md_ack_p1_tdm2ddm        ),
                                                        
.iv_md_p2               (wv_md_p2_ddm2tdm           ),
.i_md_wr_p2             (w_md_wr_p2_ddm2tdm         ),
.o_md_ack_p2            (w_md_ack_p2_tdm2ddm        ),
                                
.iv_md_p3               (wv_md_p3_ddm2tdm           ),
.i_md_wr_p3             (w_md_wr_p3_ddm2tdm         ),
.o_md_ack_p3            (w_md_ack_p3_tdm2ddm        ),
                                
.iv_md_p4               (wv_md_p4_ddm2tdm           ),
.i_md_wr_p4             (w_md_wr_p4_ddm2tdm         ),
.o_md_ack_p4            (w_md_ack_p4_tdm2ddm        ), 

.iv_md_p5               (wv_md_p5_ddm2tdm           ),
.i_md_wr_p5             (w_md_wr_p5_ddm2tdm         ),
.o_md_ack_p5            (w_md_ack_p5_tdm2ddm        ),
                                                        
.iv_md_p6               (wv_md_p6_ddm2tdm           ),
.i_md_wr_p6             (w_md_wr_p6_ddm2tdm         ),
.o_md_ack_p6            (w_md_ack_p6_tdm2ddm        ),
                                
.iv_md_p7               (wv_md_p7_ddm2tdm           ),
.i_md_wr_p7             (w_md_wr_p7_ddm2tdm         ),
.o_md_ack_p7            (w_md_ack_p7_tdm2ddm        ),
                                
.iv_md_p8               (wv_md_p8_ddm2tdm           ),
.i_md_wr_p8             (w_md_wr_p8_ddm2tdm         ),
.o_md_ack_p8            (w_md_ack_p8_tdm2ddm        ),

.iv_md_p9               (wv_md_p9_ddm2tdm           ),
.i_md_wr_p9             (w_md_wr_p9_ddm2tdm         ),
.o_md_ack_p9            (w_md_ack_p9_tdm2ddm        ),

.iv_md_p10               (wv_md_p10_ddm2tdm           ),
.i_md_wr_p10             (w_md_wr_p10_ddm2tdm         ),
.o_md_ack_p10            (w_md_ack_p10_tdm2ddm        ),

.iv_md_p11               (wv_md_p11_ddm2tdm           ),
.i_md_wr_p11             (w_md_wr_p11_ddm2tdm         ),
.o_md_ack_p11            (w_md_ack_p11_tdm2ddm        ),

.iv_md_p12               (wv_md_p12_ddm2tdm           ),
.i_md_wr_p12             (w_md_wr_p12_ddm2tdm         ),
.o_md_ack_p12            (w_md_ack_p12_tdm2ddm        ),

.iv_md_p13               (wv_md_p13_ddm2tdm           ),
.i_md_wr_p13             (w_md_wr_p13_ddm2tdm         ),
.o_md_ack_p13            (w_md_ack_p13_tdm2ddm        ),

.iv_md_p14               (wv_md_p14_ddm2tdm           ),
.i_md_wr_p14             (w_md_wr_p14_ddm2tdm         ),
.o_md_ack_p14            (w_md_ack_p14_tdm2ddm        ),

.iv_md_p15               (wv_md_p15_ddm2tdm           ),
.i_md_wr_p15             (w_md_wr_p15_ddm2tdm         ),
.o_md_ack_p15            (w_md_ack_p15_tdm2ddm        ), 

.iv_md_p16               (wv_md_p16_ddm2tdm           ),
.i_md_wr_p16             (w_md_wr_p16_ddm2tdm         ),
.o_md_ack_p16            (w_md_ack_p16_tdm2ddm        ),

.iv_md_p17               (wv_md_p17_ddm2tdm           ),
.i_md_wr_p17             (w_md_wr_p17_ddm2tdm         ),
.o_md_ack_p17            (w_md_ack_p17_tdm2ddm        ),

.iv_md_p18               (wv_md_p18_ddm2tdm           ),
.i_md_wr_p18             (w_md_wr_p18_ddm2tdm         ),
.o_md_ack_p18            (w_md_ack_p18_tdm2ddm        ),

.iv_md_p19               (wv_md_p19_ddm2tdm           ),
.i_md_wr_p19             (w_md_wr_p19_ddm2tdm         ),
.o_md_ack_p19            (w_md_ack_p19_tdm2ddm        ), 

.iv_md_p20               (wv_md_p20_ddm2tdm           ),
.i_md_wr_p20             (w_md_wr_p20_ddm2tdm         ),
.o_md_ack_p20            (w_md_ack_p20_tdm2ddm        ),

.iv_md_p21               (wv_md_p21_ddm2tdm           ),
.i_md_wr_p21             (w_md_wr_p21_ddm2tdm         ),
.o_md_ack_p21            (w_md_ack_p21_tdm2ddm        ),

.iv_md_p22               (wv_md_p22_ddm2tdm           ),
.i_md_wr_p22             (w_md_wr_p22_ddm2tdm         ),
.o_md_ack_p22            (w_md_ack_p22_tdm2ddm        ),

.iv_md_p23               (wv_md_p23_ddm2tdm           ),
.i_md_wr_p23             (w_md_wr_p23_ddm2tdm         ),
.o_md_ack_p23            (w_md_ack_p23_tdm2ddm        ), 

.iv_md_p24               (wv_md_p24_ddm2tdm           ),
.i_md_wr_p24             (w_md_wr_p24_ddm2tdm         ),
.o_md_ack_p24            (w_md_ack_p24_tdm2ddm        ),

.iv_md_p25               (wv_md_p25_ddm2tdm           ),
.i_md_wr_p25             (w_md_wr_p25_ddm2tdm         ),
.o_md_ack_p25            (w_md_ack_p25_tdm2ddm        ),

.iv_md_p26               (wv_md_p26_ddm2tdm           ),
.i_md_wr_p26             (w_md_wr_p26_ddm2tdm         ),
.o_md_ack_p26            (w_md_ack_p26_tdm2ddm        ),

.iv_md_p27               (wv_md_p27_ddm2tdm           ),
.i_md_wr_p27             (w_md_wr_p27_ddm2tdm         ),
.o_md_ack_p27            (w_md_ack_p27_tdm2ddm        ), 

.iv_md_p28               (wv_md_p28_ddm2tdm           ),
.i_md_wr_p28             (w_md_wr_p28_ddm2tdm         ),
.o_md_ack_p28            (w_md_ack_p28_tdm2ddm        ),

.iv_md_p29               (wv_md_p29_ddm2tdm           ),
.i_md_wr_p29             (w_md_wr_p29_ddm2tdm         ),
.o_md_ack_p29            (w_md_ack_p29_tdm2ddm        ),

.iv_md_p30               (wv_md_p30_ddm2tdm           ),
.i_md_wr_p30             (w_md_wr_p30_ddm2tdm         ),
.o_md_ack_p30            (w_md_ack_p30_tdm2ddm        ),

.iv_md_p31               (wv_md_p31_ddm2tdm           ),
.i_md_wr_p31             (w_md_wr_p31_ddm2tdm         ),
.o_md_ack_p31            (w_md_ack_p31_tdm2ddm        ), 

.iv_md_p32               (wv_md_p32_ddm2tdm           ),
.i_md_wr_p32             (w_md_wr_p32_ddm2tdm         ),
.o_md_ack_p32            (w_md_ack_p32_tdm2ddm        ),                          

.ov_tdm_state           (                           ),

.ov_md                  (ov_md      ),
.o_md_wr                (o_md_wr    )
);

endmodule